Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 710

Operating Mode
BUS
INTERFACE
CHIP RESET
AND
WDT_RSTO
WATCH DOG TIMER
Figure 19-1. Watchdog Timer Block Diagram
Operating Mode
The WDT operates in trip count mode as described below.
Trip Count
The WDT contains a software programmable trip counter register that
sets the number of times that the timer can expire before the
is continually asserted (until the next time hardware reset is applied). The
trip counter is not cleared by the WDT generated reset. This gives soft-
ware the ability to count the number of WDT generated resets using the
bits in the
CURTRIPVAL
19-6
www.BDTIC.com/ADI
PCLK/WDTCLK
SYNC
COUNTER AND
WDT RESET
RESET LOGIC
CLOCK GENERATOR
(Resonator/Oscillator)
WDT_CLKIN
register.
WDTTRIP
ADSP-214xx SHARC Processor Hardware Reference
DM, PM BUS
WDT REGISTERS
PCLK/WDTCLK
SYNC
WDTCLK
WDTCLKSEL
WDT_CLKO
pin
WDTRSTO