Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 931

31 30
CE
Channel x Enable
CTRAN
Channel x Transmit Select
CTYPE (29–28)
Channel x Type Select
15
FSCD
Frame Synchronization
Channel Disable
FSPC (12–8)
Frame Synchronization Physi-
cal Channel Count
Figure A-49. MLB_CECRx Register (Synchronous Channels)
Table A-67. MLB_CECRx Register Bit Descriptions for Synchronous
Channels (RW)
Bit Name
7–0 CA
12–8 FSPC
14–13 Reserved
15 FSCD
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
Description
Channel Address. These bits determine the channel address associ-
ated with this logical channel. MLB channel address is 16 bits; bits
15–9 and LSB are always zero. Only bits 8–1 vary and they are
defined by MLB_CECRx bits 7–0.
00000001 0x0002
00000010 0x0004
00000011 0x0006
00000100 0x0008
.............
11111111 0x01FE
Frame Synchronization Physical Channel Count. Defines the num-
ber of physical channels expected to match this logical channel's
channel address each MLB frame.
Frame Synchronization Channel Disable. When set, disables this
logical channel when frame synchronization is lost.
Registers Reference
21 20 19 18 17 16
MASK (23–16)
Channel x Interrupt Mask
MDS
Channel x Mode Select
FSE
Frame Synchronization
Enable
6 5 4 3 2 1 0
CA (7–0)
Channel Address
A-105