Iop Throughput; Programming Model - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Programming Model

IOP Throughput

Since the I/O processor controls two I/O buses (peripheral and external
port) the maximum bandwidth per IOD bus is gained for:
• Internal memory writes with f
• Internal memory reads with f
Table 2-30. I/O Processor TCB Chain Loading Access
Chained TCB Type
SPI DMA, SPORT DMA
IIR Accelerator DMA coefficient
IIR Accelerator DMA data
External Port standard DMA, FFT Accelerator DMA,
Delay Line DMA read
External Port Circular Buffer DMA, Delay Line DMA
write
External Port Scatter/Gather DMA
External Port Circular Buffer Scatter/Gather DMA
FIR Accelerator DMA
1 If the TCB for a SPORT is located in external memory, additional access cycles are required for
External Port arbitration and AMI or DDR2 cycles.
2 For throughput performance add 6 core cycles.
Programming Model
This section provides a general procedure for configuring DMAs. There is
more specific information on DMA in each peripheral chapter.
2-50
www.BDTIC.com/ADI
PCLK
1
, Link port DMA
2
2
2
ADSP-214xx SHARC Processor Hardware Reference
× 32-bit
PCLK
/2 × 32-bit
TCB Size
4
5
10
6
7
8
10
13
Number of Core
Cycles
26
22
40
34
40
42
50
94