Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 688

Effect Latency
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
Shift Register Effect Latency
After the SR register is configured, the maximum effect latency is 2
cycles.
Programming Model
Since the
SR_CTL
come from the peripheral clock domain (
domain, there are timing violations for one
SR_LAT_I
To avoid this program the folloing registers in the order listed.
1. The
SRU_CLK_SHREG
2. The
SR_CTL
3. Drive the
17-8
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, , and
SRU_CLK_SHREG
, and
SRU_DAT_SHREG
register.
,
SR_SDCLK_I SR_LAT_I
ADSP-214xx SHARC Processor Hardware Reference
register signals
SRU_DAT_SHREG
) to the
PCLK SR_SDCLK_I
SR_SCLK_I
registers.
, and input signals.
SR_SDI_I
PCLK
and
period.