Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 658

Features
Table 16-1. Timer Specifications (Cont'd)
Feature
DMA Chaining
Interrupt Source
Boot Capable
Local Memory
Clock Operation
Features
The peripheral timers have the features described below.
• Independent general-purpose timers
• Three operation modes (PWM, Width capture, external watchdog)
• Global control/status registers for synchronous operation of multi-
ple timers
• Buffered timer registers (Period and Width) to allow changes on
the fly

The core timer is controlled by system registers while the periph-
eral timers are controlled by memory-mapped registers.
16-2
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Timer1–0
N/A
Core
N/A
No
f
PCLK
ADSP-214xx SHARC Processor Hardware Reference