Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 904

Peripheral Registers
Multiplier Status Register (FFTMACSTAT)
The
FFT_MACSTAT
debug mode. The status bits are sticky and are cleared when read.
Table A-44. FFT_MACSTAT Register Bit Descriptions (ROC)
Bits Name
0 FFT_NAN
1 FFT_DENORM
2 FFT_OVR
3 FFT_UDR
31–4 Reserved
DMA Status Register
The bits in the status register, described in
information.
Table A-45. FFTDMASTAT Register Bit Descriptions (RO)
Bits Name
0 ICPLD
1 IDMASTAT
2 (ROC) IDMACHIRPT
3 OCPLD
4 ODMASTAT
5 (ROC) ODMACHIRPT
31–6 Reserved
A-78
www.BDTIC.com/ADI
register, described in
Description
Bits 3–0 follow the IEEE STD for floating point num-
bers.
Description
Input Chain Pointer Loading
Input DMA in Progress
Input DMA Channel Interrupt
Output Chain Pointer Loading
Output DMA in Progress
Output DMA Channel Interrupt
ADSP-214xx SHARC Processor Hardware Reference
Table A-44, can be written only in
Table A-45 report DMA status