Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 935

Table A-68. MLB_CSCRx Register Description (RO)
Bit Name
0 STS0
1 STS1
2 STS2
(I/O)
2 STS2
(DMA)
3 STS3
(I/O)
3 STS3
(DMA)
ADSP-214xx SHARC Processor Hardware Reference
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Description
Current Buffer Protocol Error. Indicates that either a TX channel has detected an
RxStatus of ReceiverProtocolError (72h), an RX channel has detected an invalid
command for a given channel type, or an additional ControlStart (30h) or Async-
Start (20h) command has been received while in the middle of a packet. The set-
ting of this bit generates a maskable channel interrupt to system software. This bit
is valid for all RX channel types and valid for only asynchronous and control TX
channels.
Current Buffer Detect Break. Indicates that either a TX channel has detected a
receiver break response, ReceiverBreak (70h), or an RX channel has detected a
transmitter break command, ControlBreak (36h) or AsyncBreak (26h), while pro-
cessing the Current Buffer. The setting of this bit generates a maskable channel
interrupt to system software. This bit is valid for asynchronous and control chan-
nels only.
Receive Service Request (I/O). Indicates that an RX channel is requesting service
from system software. Receive service requests are issued if the number of free
quadlets in the local channel buffer is less than or equal to LCBCRn.TH[9:0].
The setting of this bit generates a maskable channel interrupt to system software.
This bit is valid for all channel types.
Current Buffer Done (DMA). Indicates that the last quadlet from the last packet
(in the Current Buffer) has been successfully transmitted or received. The setting
of this bit generates a maskable channel interrupt to system software. This bit is
valid for all channel types.
Transmit Service Request. Indicates that a TX channel is requesting service from
system software. Transmit service requests are issued if the number of valid quad-
lets in the local channel buffer is less than or equal to LCBCRn.TH[9:0]. The set-
ting of this bit generates a maskable channel interrupt to system software. This bit
is valid for all channel types.
Current Buffer Start. Indicates that the DMA controller has started processing
the Current Buffer. This bit is set after the contents of CNBCRn have been
loaded into CCBCRn, the CSCRn.RDY bit has been cleared (for ping-pong buff-
ering), and hardware is available to accept the next buffer. The setting of this bit
generates a maskable channel interrupt to system software. This bit is valid for all
channel types.
Registers Reference
A-109