Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 984

Peripherals Routed Through the DAI
Table A-84. SPCTLx Register Bit Descriptions (Standard Serial Mode)
(RW) (Cont'd)
Bit Name
29 DERR_A
(RO)
31–30 DXS_A
(RO)
DXS_A (31–30)
Data Buffer Channel A Status
DERR_A
Channel A Error Status
DXS_B (28–27)
Data Buffer Channel B Status
DERR_B
Channel B Error Status
SPTRAN
SPORT Transaction
SPEN_B
SPORT Enable B
BHD
Buffer Hang Disable
15
DIFS
Data Independent Frame Sync
OPMODE
SPORT Operation Mode
MSTR
2
I S Serial and L/R Clock Master
Figure A-87. SPCTLx Register for I
A-158
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Description
Channel A Error Status (sticky). Refer to DERR_B
Channel A Data Buffer Status. Refer to DXS_B
31 30 29 28 27 26 25 24
14 13 12 11 10 9 8
ADSP-214xx SHARC Processor Hardware Reference
23 22 21 20 19 18 17 16
7 6 5 4 3 2 1 0
2
S and Left-Justified Modes
L_FIRST
Channel First Select
LAFS
OPMODE
SDEN_A
DMA Channel A Enable
SCHEN_A
DMA Channel A Chaining Enable
SDEN_B
DMA Channel B Enable
SCHEN_B
DMA Channel B Chaining Enable
SPEN_A
SPORT Enable A
SLEN (8–4)
Serial Word Length – 1
PACK
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