16-Bit Address Mapping - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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SDRAM Controller (ADSP-2147x/ADSP-2148x)

Row Address Width (SDRAW). These bits in the

mine the row width of the SDRAM. The

for row widths of 8 to 15.

Column Address Width (SDCAW). The SDRAM memory control regis-

ter also includes external bank specific programmable parameters. The

external bank can be configured for a different SDRAM size. The

SDRAM controller determines the internal SDRAM page size from the

X16DE and SDCAW parameters. Page sizes of 128, 256, 512, 1K, 2K

words are supported.

16-Bit Address Mapping

Even if the external data width is 16 bits, the processor supports only

32-bit data accesses. If

accesses to get and place 32-bit data. The SDC takes the IA address and

appends one extra bit to the LSB to generate the address externally.

In the following sections and in

ping of internal addresses to the external addresses is discussed. The

mapping of the addresses depends on the address mode (SDAD-

DRMODE) on row address width (SDRAW), and on column address

width (SDCAW).

For example, if the processor core requests address 0x200–0000 for a

32-bit access, the SDC performs two 16-bit accesses at 0x400–0000 and

0x400–0001, using

addresses seen by 16-bit SDRAMs is shown in

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is enabled (=1) the SDC performs two 16-bit

bit must always be set.

to get one 32-bit data word. The column and row

ADSP-214xx SHARC Processor Hardware Reference

bits can be programmed

= 101 (13 bits), and

3-10, the map-

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