Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 930

Peripheral Registers
Table A-66. MLB_CECRx Register Bit Descriptions for Asynchronous
and Control Channels (RW) (Cont'd)
Bit Name
20 MASK4
21 Reserved
22 MASK6
23 MASK7
24 Reserved
26–25 MDS
27 PCE
29–28 CTYPE
30 CTRAN
31 CE
A-104
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Description
Mask Buffer Error. When set, masks buffer error channel interrupts
for this logical channel.
Mask Lost Frame Synchronization. When set, masks lost frame syn-
chronization channel interrupts for this logical channel.
Reserved
Channel x Mode Select.
00 = Ping-pong DMA mode (default)
01 = Circular buffering DMA
10 = I/O mode enable
11 = Reserved
Packet Count Enable. Enable the Rx packet counter. This bit is valid
for asynchronous and control Rx channels in I/O mode.
0 = Disable
1 = Enable
Channel x Type Select.
00 = Synchronous (default)
01 = Reserved
10 = Asynchronous
11 = Control
Channel x Transmit Select.
0 = Receive (default)
1 = Transmit
Channel x Enable.
0 = Channel n disabled (default)
1 = Enabled
ADSP-214xx SHARC Processor Hardware Reference