Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 943

Table A-74. WDTCLKSEL Register Bit Descriptions (RW) (Cont'd)
Bit Name
1 OSCPWRDWN
2 OSCRST
Period (WDTCNT)
The register, shown in Table 3, holds the 32-bit unsigned count
WDTCNT
value. The
WDTCNT
read/writes.
The watchdog count register holds the programmable count value. A valid
write to the watchdog count register also preloads the watchdog current
counter. For added safety, the watchdog count register can only be
updated when the WDT is disabled and WDT configuration space is
unlocked by programming the command in the
Unlock (WDTUNLOCK)
The
WDTUNLOCK
accidental writes from the processor core. Before attempting to write to
the WDT configuration space, the core must unlock the WDT by writing
the command value (0xAD21AD21) to this register. Attempts by the core
to write to WDT configuration space without this command causes the
WDT to expire. This exception is captured in the
After configuring the WDT configuration space, the core needs to lock it
again by writing any value other than the command value to the
register.
LOCK
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Description
Internal RC Oscillator Power Down.
0 = Oscillator is powered up
1 = Oscillator is powered down
Internal RC Oscillator Reset.
0 = Oscillator is reset
1 = Oscillator out of reset
register must always be accessed with 32-bit
register protects the WDT configuration space against
Registers Reference
register.
WDTUNLOCK
register.
WDTSTATUS
WDTUN-
A-117