Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 503

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Each transmitter and receiver has its own DMA registers. The same DMA

channel drives the left and right I

receiver. The software application must stop multiplexing the left and

right channel data received by the receive buffer, because the left and right

data are interleaved in the DMA buffers.

Channel A and B on each SPORT share a common interrupt vector. The

DMA controller generates an interrupt at the end of DMA transfer only.

Figure 10-5 on page 10-28

(word select), serial clock, and I

as for frame sync.

The value of the

the receive or transmit register for the SPORT becomes active.

The SPORT DMA channels are assigned higher priority than all other

DMA channels (for example, the SPI port) because of their relatively low

service rate and their inability to hold off incoming data. Having higher

priority causes the SPORT DMA transfers to be performed first when

multiple DMA requests occur in the same cycle. The serial port DMA

channels are numbered and prioritized as shown in

Although the DMA transfers are performed with 32-bit words, serial ports

can handle word sizes from 3 to 32 bits, with 8 to 32 bits for I

serial words are 16 bits or smaller, they can be packed into 32-bit words

for each DMA transfer. DMA transfers are configured using the

registers. When serial port data packing is enabled (

1), the transmit and receive interrupts are generated for the 32-bit packed

words, not for each 16-bit word.

External Memory DMA Transfers

In previous SHARC processors, transferring data from a SPORT to exter-

nal memory required placing that data temporarily in internal memory

ADSP-214xx SHARC Processor Hardware Reference

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S channels for the transmitter or the

shows the relationship between frame sync

S data. Timing for word select is the same

) determines whether

Table 2-28 on

Serial Ports

Chapters

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