Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 635

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in the registers are zeros. This code works only if the
both the transmitter and receiver, and the
= 1 in the transmitter and receiver, and
received words follow the order 0x12, 0x34, 0x56, 0x78.
16-bit word. When transmitting, the SPI port sends out only the lower 16
bits of the word written to the SPI buffer. When receiving, the SPI port
packs the 16-bit word to the lower 32 bits of the
upper bits in the register are zeros.
32-bit word. No packing of the
entire 32-bit register is used for the data word.
Core Buffer Status
For core access to SPI, master and slave mode operates different:
1. If core access to a SPI slave is unable to keep up with the trans-
mit/receive stream during a transfer operation (because of an
interrupt or any other reason) the SPI operates according to the
states of the
• If
repeatedly transmits zeros on the
transmitted for each new transfer initiate command.
• If
repeatedly transmits the last word transmitted before the
transmit buffer became empty.
• If
to receive new data from the
data in the
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
RXSPI
and
bits in the
SENDZ
GM
= 1 and the transmit buffer is empty, the device
SENDZ
= 0 and the transmit buffer is empty, the device
SENDZ
= 1 and the receive buffer is full, the device continues
GM
buffer.
RXSPI
Serial Peripheral Interface Ports
MSBF
frequency is less. If
SPICLK
has a lower frequency, the
SPICLK
RXSPI
or
registers is necessary as the
TXSPI
register.
SPICTLx
pin. One word is
MOSI
pin, overwriting the older
MISO
bit is zero in
MSBF
buffer while the
15-19

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