Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 867

Table A-20. DLL0CTL1 Register Bit Descriptions (RW)
Bit Name
8–0 Reserved
9 RESETDLL
10 RESETDAT
11 RESETCAL
31–12 Reserved
DLL1 Control Register 1 (DLL1CTL1)
The register shown in
DLL1CTL1
includes the programmable parameters associated with the DLL1 device.
Note that it takes at least 9 core clock cycles to perform a DLL reset.
RESETCAL
Reset the DQS Phase Cali-
bration Logic
Figure A-17. DLL1CTL1 Register
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Description
Reset DLL Control Logic. Active high, when active, it resets the
DLL control logic only, including the 90 degree DQS shifters.
0 = No effect
1 = Reset DLL0 control logic
Reset Data Capture Logic. Active high, when active, it resets the
data capture logic only, including P and N buffers.
0 = No effect
1 = Reset DLL0 data capturel logic
Reset DQS Phase Calibration Logic. Active high, when active, it
resets the DQS phase calibration logic.
0 = No effect
1 = Reset DLL0 DQS phase calibration logic
Figure A-17
31 30 29 28 27 26 25 24
15 14 13 12 11 10 9 8
Registers Reference
and described in
23 22 21 20 19 18 17 16
7 6 5 4 3 2 1 0
Table A-21
RESETDLL
Reset DLL Control Logic
RESETDAT
Reset Data Capture Logic
A-41