Standard Dma Parameter Registers - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

DMA Channel Registers

Standard DMA Parameter Registers

The parameter registers described below control the source and destina-
tion of the data, the size of the data buffer, and the step size used.

The length of DMA registers for the serial ports have changed from
earlier SHARC processors in order to accommodate data transfers
to/from external memory.
Index registers. These registers, shown in
memory address that acts as a pointer to the next internal memory DMA
read or write location. All internal index addresses are based on an internal
memory offset of 0x80000.
Table 2-2. Index Registers
Register Name
IISP0–7A
IISP0–7B
IISPI
IISPIB
IDP_DMA_I0–7
IDP_DMA_I0–7A
IDP_DMA_I0–7B
IIUART0RX
IIUART0TX
IILB0–1
IIFIR
CIFIR
OIFIR
IIIIR
CIIIR
2-4
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Width (Bits) Description
28 SPORTxA (supports external addresses)
28 SPORTxB (supports external addresses)
19 SPI
19 SPIB
19 IDPx
19 IDPx index A (ping pong)
19 IDPx index B (ping pong)
19 UART0 Receiver
19 UART0 Transmitter
19 Link Port0–1
19 Accelerator FIR data input
19 Accelerator FIR coeff input
19 Accelerator FIR output
19 Accelerator IIR data input
19 Accelerator IIR coeff input
ADSP-214xx SHARC Processor Hardware Reference
Table 2-2, provide an internal