Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 117

Table 2-28. DMA Channel 0–66 Priorities (Cont'd)
DMA Peripheral
Channel Group
Number
17 D
18
19
20 E
21–51 F
52 G
53 H
54 I
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Control/Status Parameter
Registers Registers
IDP_CTL, IDP_DMA_I5,
IDP_CTL1, IDP_DMA_M5,
IDP_CTL2, IDP_DMA_C5,
IDP_PP_CTL, IDP_DMA_I5A,
DAI_STAT IDP_DMA_I5B,
IDP_DMA_PC5
IDP_DMA_I6,
IDP_DMA_M6,
IDP_DMA_C6,
IDP_DMA_I6A,
IDP_DMA_I6B,
IDP_DMA_PC6
IDP_DMA_I7,
IDP_DMA_M7,
IDP_DMA_C7,
IDP_DMA_I7A,
IDP_DMA_I7B,
IDP_DMA_PC7
SPICTL, IISPI, IMSPI,
SPIDMAC, CSPI, CPSPI
SPIBAUD
SPISTAT
MLB_xCR
SPICTLB, IISPIB, IMSPIB,
SPIDMACB, CSPIB, CPSPIB
SPIBAUDB,
SPISTATB
MTMCTL (or IIMTMW,
DTCP) IMMTMW,
CMTMW
IIMTMR,
IMMTMR,
CMTMR
I/O Processor
Data Buffer Description
IDP_FIFO Serial Input DAI
IDP Channel 5
Serial Input DAI
IDP Channel 6
Serial Input DAI
IDP Channel 7
RXSPI or TXSPI SPI Data
and DMA Buffer
Local SRAM Buf- MLB Data
fer
RXSPIB or SPI B Data
TXSPIB and
DMA Buffer
MTM FIFO Memory-to-
memory write data
MTM FIFO Memory-to-
memory read data
2-39