Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 475

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1. Serial clock (

2. Frame sync (

Frames define the required data length (after the serial to parallel conver-

sion) necessary to store the data in memory for further processing as

sync called master while the receiver is slave sampling these data.

Figure 10-3. Frame Sync and Data Driven on Rising Edge

After the slave is sampled the

maximum setting. Each

frame is received. If the transmitter drives the frame sync and data on the

rising edge, the falling edge is used to sample the frame sync and data, and

ADSP-214xx SHARC Processor Hardware Reference

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the SPORT uses two control signals to sample

) applies the bit clock for each serial data.

) divides the incoming data stream into frames.

10-3. The transmitter for example drives clock and frame

decrements the

word counter is reloaded to the

counter until the full

Serial Ports

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