Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 942

Peripheral Registers
updated when the WDT is disabled and WDT configuration space is
unlocked by programming the command in the
Table A-73. WDTTRIP Register Bit Descriptions (RW)
Bit Name
3–0 TRIPVAL
7–4 (RO) CURTRIPVAL
Clock Select (WDTCLKSEL)
This register, described in
WDT is disabled and WDT configuration space is unlocked by program-
ming the command in the
register are ignored after the WDT is enabled.
Note: This register is reset on external hardware reset only. This ensures
that the selected clock source remains the same even after a WDT gener-
ated reset is asserted.
Table A-74. WDTCLKSEL Register Bit Descriptions (RW)
Bit Name
0 CLKSEL
A-116
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Description
Current Value of Trip Counter. This is the trip counter
value, programmable from 0 to 15. The number of times
WDT can expire is programmable by the TRIPVAL field
Reading this register also gives the current value of the trip
counter.
Current Number of WDT Resets. Reports all current WDT
generated resets (
Table A-74, can only be updated when the
register. Writes to the
WDTUNLOCK
Description
Clock Select. When this bit = 0, the WDTCLK source can
be an external clock applied to the WDT_CLKIN pin or an
external ceramic Oscillator connected to the WDT_CLKIN
and WDT_CLKO pins.
0 = Selects ceramic oscillator output or external clock
1 = Selects internal RC oscillator output
ADSP-214xx SHARC Processor Hardware Reference
register.
WDTUNLOCK
asserted).
WDTRSTO
WDTCLKSEL