Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 507

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• In standard mode the

the conditions of whether both channels are logically ANDed or

• For all other operating modes, channels A and B are logically

ANDed. If both channels are enabled, both buffers need to be

updated by the DMA controller to drive data and frame sync

Note that for all operating modes, if the

transfers have completed, the frame sync continues to drive off-chip and

the data output are zero with the

This section handles the various scenarios in which an interrupt is trig-

gered. Both the core and DMA are able to generate data interrupts for

receive or transmit operations. Moreover, the SPORT modules generate

error conditions which generate a separate interrupt.

provides an overview of SPORT interrupts.

Table 10-10. SPORT Interrupt Overview

Interrupt Source

SPORT (standard,

I2S, left justified,

packed, multichan-

nel, 16 channels)

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Interrupt Condition

– DMA RX/TX done

– Core RX buffer full

– Core TX buffer empty

– DMA under/overflow

– Frame sync error

bit is set and the DMA

Internal transfer

RTI instruction

or access comple-

Serial Ports

Chapters

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