Clocking Options; Frame Sync Options - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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Operation Modes
The serial port can automatically select some words for particular channels
while ignoring others. Up to 128 channels are available for transmitting or
receiving or both. Each SPORT can receive or transmit data selectively
from any of the 128 channels.
Data companding and DMA transfers can also be used in multichannel
mode on channel A. Channel B can also be used in multichannel mode,
but companding is not available on this channel.
Although the eight SPORTs are programmable for data direction in the
standard mode of operation, their programmability is restricted for multi-
channel operations. The following points summarize these limitations:
1. The primary A channels of SPORT1, 3, 5, and 7 are capable of
expansion only, and the primary A channels of SPORT0, 2, 4, and
6 are capable of compression only.
2. Receive comparison is not supported.

Clocking Options

In multichannel mode, the serial ports can either accept an external serial
clock or generate it internally. The
determines the selection of these options. For internally-generated serial
clocks, the
CLKDIV
Finally, programs can select whether the serial clock rising edge is used for
sampling or driving serial data and/or frame syncs. This selection is per-
formed using the

Frame Sync Options

In previous SHARC processors, multichannel mode required a SPORT
pair. This pair was needed to route the
frame sync to the odd SPORT. The pair itself interconnect the
signals.
FS
10-32
www.BDTIC.com/ADI
ICLK
bits in the
register configure the serial clock rate.
DIVx
bit in the
CKRE
SPCTL
ADSP-214xx SHARC Processor Hardware Reference
bit in the
register
SPCTL
register.
on the even SPORT and the
SCLK
and
SCLK

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