Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 967

DAI Pin Buffer Enable Registers
(SRU_PBENx, Group F)
The pin enable control registers (see
Table A-80) activate the drive buffer for each of the 20 DAI pins. When
the pins are not enabled (driven), they can be used as inputs.
PBEN05_I
DAI Port 5
Pin Buffer Enable Input
15
PBEN03_I
PBEN02_I
DAI Port 2
Pin Buffer Enable Input
Figure A-77. SRU_PBEN0 (RW)
PBEN10_I
DAI Port 10
Pin Buffer Enable Input
PBEN08_I
PBEN07_I
DAI Port 7
Pin Buffer Enable Input
Figure A-78. SRU_PBEN1 (RW)
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
31 30 29 28 27 26 25 24
14 13 12 11 10 9 8
31 30 29 28 27 26 25 24
15 14 13 12 11 10 9 8
Registers Reference
Figure A-77 through
23 22 21 20 19 18 17 16
7 6 5 4 3 2 1 0
23 22 21 20 19 18 17 16
7 6 5 4 3 2 1
Figure A-80,
PBEN03_I (23–18) (con't)
DAI Port 3
Pin Buffer Enable Input
PBEN04_I
DAI Port 4
Pin Buffer Enable Input
PBEN01_I
DAI Port 1
Pin Buffer Enable Input
PBEN08_I (23–18) (con't)
DAI Port 8
Pin Buffer Enable Input
PBEN09_I
DAI Port 9
Pin Buffer Enable Input
0
PBEN06_I
DAI Port 6
Pin Buffer Enable Input
A-141