Register Overview - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Register Overview

The SRU for the DAI contains six register sets that are associated with the
DAI groups.
Clock Routing Registers (SRU_CLKx). Associated with Group A, routes
clock signals.
Serial Data Routing Registers (SRU_DATx). Associated with group B,
routes data.
Frame Sync Routing Control Registers (SRU_FSx). Associated with
group C, routes frame syncs or word clocks to the serial ports, the SRC,
the S/PDIF, and the IDP.
Pin Signal Assignment Registers (SRU_PINx). Associated with group D,
routes physical pins (connected to a bonded pad).
Miscellaneous Signal Routing Registers (SRU_MISCx). Associated with
group E, allows programs to route to the DAI interrupt latch, PBEN
input routing, or input signal inversion.
DAI Pin Buffer Enable Registers (SRU_PBENx). Associated with group
F, Activate the drive buffer for each of the 20 DAI pins.
DAI Shift Registers (SRU_PBENx). Associated with group G, routes all
shift register signals.
The SRU2 for DPI contains three register sets associated with the DPI
groups.
Miscellaneous Signal Routing Registers (SRU2_INPUTx). Associated
with group A, used to route the 14 external pin signals to the inputs of the
other peripherals.
Pin Assignment Signal Routing (SRU2_PINx). Associated with group B
routes pin output signals to the DPI pins.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Digital Application/Digital Peripheral Interfaces
9-3