Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 855

Table A-11. DDR2CTL0 Register Bit Descriptions (RW) (Cont'd)
Bit Name
27 DDR2OPT
31–28 DDR2MODIFY
DDR2 Timing Control Register 1 (DDR2CTL1)
The register includes the programmable parameters associated
DDR2CTL1
with the DDR access timing.
timing control bit definitions. All the values are defined in terms of num-
ber of clock cycles.
31 30
DDR2TFAW (29–25)
tFAW Setting
15
DDR2TRCD (15–12)
tRCD Setting
DDR2TWTR (11–9)
tWTR Setting
Figure A-10. DDR2CTL1 Register
ADSP-214xx SHARC Processor Hardware Reference
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Description
Read Optimization Enable.
0 = Disable read optimization
1 = Enable read optimization
Read Modifier (In Optimization Mode).
0000 = Modifier 0
0001 = Modifier 1
...
1111 = Modifier 15
Note that these bits only are used in SISD mode.
Figure A-10
29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
Registers Reference
and Table A-12
21 20 19 18 17 16
6 5 4 3 2 1 0
show the DDR
DDR2TRTP (21–19)
tRTP Setting
DDR2TRRD (24–22)
tRRD Setting
DDR2TRAS (4–0)
tRAS Setting
DDR2TRP (8–5)
tRP Setting
A-29