Link Port Transmit Dma Register; Link Port Receive Dma Register - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Link Port Transmit DMA Register

Table 2-17. Link Port Transmit DMA Register
Register Quad Link Output DMA TCBs
(DMA channels 4, 5, 6, 7)
DMA channel 4
DC4
DMA channel 5
DC5
DMA channel 6
DC6
DMA channel 7
DC7
Reserved
1 DMA registers can be accessed only as quad-words.

Link Port Receive DMA Register

Table 2-18. Link Port Receive DMA Register
Register Link Input and IFIFO DMA TCBs
Quad (DMA channels 8, 9, 10, 11, 12, 13)
DMA channel 8
DC8
DMA channel 9
DC9
DMA channel 10
DC10
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Direct Memory Address Remarks
0x180420 - 3
TCB
0x180424 - 7
TCB
0x180428 - B
TCB
0x18042C - F
TCB
0x180430 - 3
TCB
TCB
TCB
Memory and Register Map
1
1
1
1
Direct Memory Address
0x180440
0x180441
0x180442
0x180443
0x180444
0x180445
0x180446
0x180447
0x180448
0x180449
0x18044A
0x18044B
1
Reset Value
0x5780 0000
0x0000 0000
0x0100 0004
0x0000 0000
0x5780 0000
0x0000 0000
0x0100 0004
0x0000 0000
0x5780 0000
0x0000 0000
0x0100 0004
0x0000 0000
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