Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 729

Table 20-4. UART Interrupt Overview
Interrupt Interrupt Condition
Source
DPI UART – DMA RX/TX done
(TX/RX) – Core RX buffer full
– Core TX buffer empty
– Core RX Error (overrun,
parity, framing, break)
– DMA RX Error (overrun,
parity, framing)
– Core/DMA 9-bit
addressing
UART – DMA RX/TX done
(TX/RX) – Core RX buffer full
– Core TX buffer empty
– Core RX Error (overrun,
parity, framing, break)
– DMA RX Error (overrun,
parity, framing)
– Core/DMA 9-bit
addressing
Interrupt Routing
The following sections describe the various possibilities for routing a
UART interrupt to the interrupt vector table (IVT).
DPI
The UART interrupts are all combined into the digital peripheral inter-
face (DPI) interrupt. The
interrupt is for the transmitter or receiver.
of how to enable the UART over the DPI.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Interrupt
Completion
Internal transfer
completion
Internal transfer
completion
register determines whether an
DPI_IRPTL
Listing 20-1
UART Port Controller
Interrupt Default IVT
Acknowledge
For UART DMA: P14I
Read to clear
DPI_IMASK
+ RTI instruction
For UART core
(RX INT): Read
to clear
UARTxIIR + RTI
instruction
For UART DMA: Need to route
RTI instruction UARTTXI
For UART core UARTRXI
(RX INT): Read (PICRx) to
to clear any PxxI
UARTxIIR + RTI
instruction
shows an example
20-15