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Data Transfer
Conditional Instructions
On the SHARC processors, almost all instruction types can be condi-
tional. Access to external data based on a conditional instructions are
allowed. For example:
r10=pass r9;
If EQ r4=r2+r3, r2=dm(i6,m6);
The instruction is only executed if the condition is true.
SIMD Access
The SHARC processor supports SIMD data access from external DDR2
memory. In SIMD mode, the core expects 64-bit data on a single read
request and drives 64-bit data for write requests. The controller decodes
the access request and if it is a SIMD read from a location N, the control-
ler fetches data from N and N+1, irrespective of whether N is an odd or an
even address.
The memory controller then packs the data into 64 bits and sends it back
along the core buses. For a SIMD write, the controller unpacks the 64-bit
data given by the core and writes it to N and N+1 memory locations. For
a SIMD read, the controller reads the physical data from N and N+3
memory locations and packs the 64-bit data to N and N+1 memory
locations.
The behavior of SIMD access to/from external memory is similar to the
internal processor memory. The only difference is that it is supported in
normal word (32-bit) address space only. Unlike internal memory access,
SIMD access from external memory may have a different latency, the
explicit transfer terminate first followed by the implicit transfer.
SDRAM
SIMD Mode transfers can be performed within 2 core access.
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ADSP-214xx SHARC Processor Hardware Reference
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