Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 568

Interrupts
A 12-bit counter, clocked by
attenuation. Therefore, the time it takes from the assertion of
–144 dB, full mute attenuation is 4096 FS cycles.
Likewise, the time it takes to reach 0 dB mute attenuation from the deas-
sertion of
MUTE_IN
Hard Mute
When the
SRCx_HARD_MUTE
diately mutes the input data to the SRC FIFO to zero, (–144 dB)
attenuation.
Auto Mute
When the
SRCx_AUTO_MUTE
municates with the S/PDIF receiver peripheral to determine when the
input should mute. Each SRC is connected to the S/PDIF receiver to read
the
DIR_NOAUDIO
immediately mutes the input data to the SRC FIFO to zero, (–144 dB)
attenuation.
This mode is useful for automatic detection of non-PCM audio data
received from the S/PDIF receiver.
Interrupts
The SRC mute-out signal can be used to generate interrupts on their ris-
ing edge, falling edge, or both, depending on how the DAI interrupt mask
registers (
DAI_IMASK_RE
of /
DAIHI DAILI
The
SRCx_MUTE_OUT
locked (after 4096 FS input samples) and after changes to the sample
12-16
www.BDTIC.com/ADI
SRCx_FS_IP_I
is 4096 FS cycles.
bit in the
bit in the
bits. When the
DIR_NOAUDIO
/ ) are programmed. This allows the generation
FE
interrupts either entering mute, exiting muting or both.
interrupt is generated only once when the SRC is
ADSP-214xx SHARC Processor Hardware Reference
, is used to control the mute
register is set, the SRC imme-
SRCCTL
register is set, the SRC com-
SRCCTLx
bit is set (=1), the SRC
to
MUTE_IN