Data Transfer .............................................................................. 4-13
Link Buffers .......................................................................... 4-13
Transmit Buffer ................................................................. 4-14
Receive Buffer ................................................................... 4-14
Buffer Status ..................................................................... 4-15
Core Transfers ....................................................................... 4-15
DMA Transfers ...................................................................... 4-16
Interrupts ................................................................................... 4-16
Interrupt Sources ................................................................... 4-17
Interrupt Service ................................................................... 4-17
DMA Access .......................................................................... 4-19
Chained DMA .................................................................. 4-19
Core Access ........................................................................... 4-19
Debug Features ........................................................................... 4-21
Shadow Register .................................................................... 4-21
Effect Latency ............................................................................. 4-22
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Contents
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