Bank Activation; Single Precharge - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

ing 1 to the
SDPSS
initiate the power-up sequence. The exact order of the power-up sequence
is determined by the
The load mode register command initializes the following parameters.
• Burst length = 1, bits 2–0, always zero
• Wrap type = sequential, bit 3, always zero
• Ltmode = latency mode (CAS latency), bits 6–4, programmable in
the
SDCTL
• Bits 14–7, always zero
While executing the load mode register command, the unused address
pins are set to zero. During the first
ister, the SDC issues only

Bank Activation

The bank activation command is required for first access to any internal
bank in SDRAM. This command open a row in the particular bank for
the subsequent access. The value on the
And the address provided on the
remains open for access until a single precharge command is issued to that
bank. The single precharge command must be issued before opening a dif-
ferent row in the same bank.

Single Precharge

For a page miss during reads or writes in any specific internal SDRAM
bank, the SDC uses the single precharge command to close that bank. All
other internal banks are untouched.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
bit in the register, subsequent SDRAM accesses
SDCTL
bit of the
SDPM
register
commands to satisfy the t
NOP
ADDR15–0
register.
SDCTL
cycle following load mode reg-
SDCLK
pins selects the bank.
ADDR18–17
pins selects the row. This row
External Port
specification.
MRD
3-21