Master Frame Sync - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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frame sync (

signals are configured as receivers. Likewise, the frame sync

considered a transmit frame sync if the data signals are configured as

transmitters. The divisor is a 15-bit value, (bit 0 in divisor register is

reserved) allowing a wide range of serial clock rates. Use the following

equation to calculate the serial clock frequency:

Transmit master: SCLK = PCLK ÷ (4(CLKDIV + 1))

Receive master: SCLK = PCLK ÷ (8(CLKDIV + 1))

The maximum serial clock frequency is equal to one-fourth (0.25) the

processor's internal peripheral clock (

is set to zero. Use the following equation to determine the value of

CLKDIV = (PCLK

If the serial clock of SPORT (

a system, only the

must be programmed.

Master Frame Sync

The bit field

counted before a frame sync pulse is generated. In this way, a frame sync

can initiate periodic transfers. The counting of serial clock cycles applies

to internally- or externally-generated serial clocks. The formula for the

number of cycles between frame sync pulses is:

Number of serial clocks between frame syncs = FSDIV + 1

Use the following equation to determine the value of

serial clock frequency and desired frame sync frequency:

FSDIV = (SCLK

ADSP-214xx SHARC Processor Hardware Reference

www.BDTIC.com/ADI

) is considered a receive frame sync if the data

frequency and desired serial clock frequency:

) is required as general-purpose clock in

bit and the serial clock divider register

specifies how many transmit or receive clock cycles are

) frequency, which occurs when

Serial Ports

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