Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 907

Table A-47. FIRCTL1 Register Bit Descriptions (RW) (Cont'd)
Bits
11
12
13
16–14
31–17
Channel Control Register (FIRCTL2)
The register, shown in
FIRCTL2
is used to configure the channel specific parameters such as filter TAP
length, window size, sample rate conversion, up/down sampling and ratio.
ADSP-214xx SHARC Processor Hardware Reference
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Name Description
FIR_CCINTR Channel Complete Interrupt.
0 = Interrupt is generated only when all channels are done
(default)
1= Interrupt is generated after each channel is done
FIR_FXD Fixed-Point Accelerator Select.
0 = 32-bit IEEE floating-point
1 = 32-bit fixed point
FIR_TC Two's-Complement Format Input Select For Fixed-Point
Mode.
0 = Unsigned integer
1 = Signed intiger
FIR_RND Rounding Mode Select For Floating-Point Mode.
000 = IEEE round to nearest (even)
001 = IEEE round to zero
010 = IEEE round to +ve infinity
011 = IEEE round to -ve infinity
100 = Round to nearest Up
101 = Round away from zero
110 = Reserved
111 = Reserved
Reserved
Figure A-36
Registers Reference
and described in Table A-48,
A-81