Dpi Interrupt Acknowledge; Core Versus Dai/Dpi Interrupts - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

latched in one of the
viced before executing an RTI instruction.
see "Interrupt Controller Registers" on page A-149.

DPI Interrupt Acknowledge

Any asynchronous or synchronous interrupt causes a latency, since it
forces the core to stop processing an instruction in process, then vector to
the interrupt service routine (ISR), (which is basically an interrupt vector
table (IVT) lookup), then proceed to implement the instruction refer-
enced in the IVT.

The DPI triggers one interrupt in the primary IVT.
When a DPI interrupt occurs, the
the 12 interrupt sources requires service.

Reading the DPI's interrupt latches (
rupts (Read-to-Clear bit type). Therefore, the ISR must service all
the interrupt sources it discovers. That is, if multiple interrupts are
latched in one of the registers, all of them must be serviced before
executing an RTI instruction.
For UART and TWI interrupts in core operation, the interrupt acknowl-
edge mechanisms may be different. For more information, refer to the
specific chapters
Wire Interface

Core versus DAI/DPI Interrupts

A pair of registers (
mally performed by the
specifies to which latch these interrupts are mapped.
Two registers (
DAI_IMASK_RE
eral's version of the
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Digital Application/Digital Peripheral Interfaces
DAI_IMASK_x
(Chapter 20, UART Port
Controller).
and
DAI_IRPTL_H
register. A single register (
IRPTL
and
DAI_MASK_FE
register. As with the
IMASK
registers, all of them must be ser-
For more information,
register determines which of
DPI_IMASK
DPI_IMASK
Controller,
) replace functions nor-
DAI_IRPTL_L
) replace the DAI periph-
IMASK
) clears the inter-
Chapter 21, Two
)
DAI_IRPTL_PRI
register, these DAI
9-39