Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 597

• Bypass mode for external frame sync manipulation
• External trigger mode starts PCG operation. No additional jitter
introduced since operation is independent of the on-chip PLL by
using off-chip clocks.
Pin Descriptions
Table 14-2 provides the pin descriptions for the PCGs. Note x = unit
A/B/C/D.
Table 14-2. PCG Pin Descriptions
Internal Nodes
Inputs
CLKIN
PCLK
PCG_SYNC_CLKx_I
PCG_EXTx_I
MISCA2_I
MISCA3_I
MISCA4_I
MISCA5_I
Outputs
PCG_CLKx_O
PCG_FSx_O
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
I/O Description
I External clock input for PCG x
I Internal peripheral clock input for PCG x
I External trigger used to enable the frame sync output
I External clock A input provided to the PCG x (not
CLKIN)
I External frame sync used for bypass mode PCG A
I External frame sync used for bypass mode PCG B
I External frame sync used for bypass mode PCG C
I External frame sync used for bypass mode PCG D
O Serial clock x output
O Frame sync x output
Precision Clock Generator
14-3