Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 193

For example, if the processor core requests address 0x20 0000 for a 32-bit
access, thecontroller performs two 16-bit accesses at 0x40 0000 and 0x40
0001, using MS0 to get one 32-bit data word.

The
X16DE
Address Map Tables
The row address and column address mappings for 16-bit addresses are
shown in Table 3-12
addresses are multiplexed to the A18–A0 pins of the processor.
Table 3-12 through
address [IA] to the external address. The mapping of the address depends
on row address width, column address width, the number of internal
banks, and the external I/O width.
Table 3-11 shows
(10), = 10.
DDR2BC
Table 3-12. 16-bit Address Mapping (8 Banks, Page Interleaving)
SHARC Pin
DDR2_BA2
DDR2_BA1
DDR2_BA0
DDR2_ADDR[12]
DDR2_ADDR[11]
DDR2_ADDR[10]
DDR2_ADDR[9]
DDR2_ADDR[8]
DDR2_ADDR[7]
DDR2_ADDR[6]
DDR2_ADDR[5]
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
bit must always be set.
through Table
Table 3-15 also show the mapping of the internal
= 0,
DDR2ADDRMODE
Column Address Row Address
IA[23]
IA[22]
IA[8] IA[21]
IA[7] IA[20]
IA[6] IA[19]
IA[5] IA[18]
IA[4] IA[17]
3-15. The row, bank and column
= 100 (12),
DDR2RAW
Bank Address
IA[11]
IA[10]
IA[9]
External Port
= 10
DDR2CAW
DDR2 Pin
BA[2]
BA[1]
BA[0]
A[12]
A[11]
A[10]
A[9]
A[8]
A[7]
A[6]
A[5]
3-63