External Instruction Fetch Throughput - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

external DDR2 memory. The throughput numbers shown are measured
by running a loop of 1024 read/writes (512 in case of SIMD reads/writes).
For the analysis, 16-bit DDR2 is used (t
t =3, t =3, t
MRD RCD
Throughput is calculated from start of the first iteration of the loop to the
end of the last iteration of the loop.
Table 3-32. Core Throughput, 400 MHz Core Clock
Operation
Core Reads (SISD/SIMD)
Core Writes (SISD)
Core Writes (SIMD)

External Instruction Fetch Throughput

The actual throughput execution from external SDRAM is dependent on
the configuration of the SDRAM. The SDRAM can be programmed to
run at a number of different frequency ratios with respect to the core
clock, the fastest being half of the core clock (or the same as the peripheral
clock). The core and SDRAM controller have been enhanced so that
throughput is maximized when SDRAM is programmed to run at half the
core clock frequency and the instructions being fetched are sequential.

Read optimization logic does not apply to external code execution.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
=1, t =3, t
WTR RP RAS
DDR2 Clock
133 MHz
200 MHz
133 MHz
200 MHz
133 MHz
200 MHz
=10, t =2, t
FAW RRD
=8, CL=4, AL=4, t
Clock Ratio Throughput
1:3 495M bytes/sec.
1:2 742M bytes/sec.
1:3 529M bytes/sec.
1:2 793M bytes/sec.
1:3 531M bytes/sec.
1:2 796M bytes/sec.
External Port
=2,
RTP
=4).
WR
3-119