Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 861

DDR2 Control Register 4 (DDR2CTL4)
The register includes the programmable parameters associated
DDR2CTL4
with the DDR2 extended mode register 2 (
DDR2 control register bit definition. All the values are defined in terms of
number of clock cycles. Values written into this register are loaded into
the DDR2 extended mode register 3 during power up (or when the force
EMR bit in the
before starting the initialization sequence.

This register's contents should not be changed while DDR2 inter-
face is active. Also whenever this register contents are changed an
initialization sequence must be executed to reflect this register con-
tents in to the DDR2 extended mode register 3.
Table A-15. DDR2CTL4 Register Bit Descriptions (RW)
Bit
13–0
15–14
DDR2 Control Register 5 (DDR2CTL5)
The register includes the programmable parameters associated
DDR2CTL5
with the DDR2 extended mode register 3 (
DDR2 control register bit definition. All the values are defined in terms of
number of clock cycles. Values written into this register are loaded into
the register during power up (or when the
DDR2EMR2
is set). This register should be initialized before starting the ini-
DDR2CTL0
tialization sequence.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
register is set). This register should be initialized
DDR2CTL0
Name Description
Reserved.
DDR2EXTMR2 Extended Mode Register 2.
Must be set to 10.
Registers Reference
). Table A-15 shows the
EMR2
).Table A-16 shows the
EMR3
Force EMR
bit in
A-35