Timing Parameters; Fixed Timing Parameters - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

The same SDRAM with page interleaving (
lowing address map:
0x200000 logical start address int bankA
0x2000FF logical end address int bankA
0x200100 logical start address int bankB
0x2001FF logical end address int bankB
0x200200 logical start address int bankC
0x2002FF logical end address int bankC
0x200300 logical start address int bankD
0x2003FF logical end address int bankD

Timing Parameters

The controller requires many timing settings in order to correctly access
the SDRAM devices. Those that are user configurable can be found in
"SDRAM Registers" on page

Fixed Timing Parameters

The timing specifications below are fixed by the controller.
• t (mode register delay). Required delay time to complete the
MRD
mode register write. This parameter is fixed to 2 cycles.
• t (row active A to row active B delay). Required delay between
RRD
two different SDRAM banks. This parameter is fixed to t
cycle.
• t (row access cycle). Required delay time to open and close a sin-
RC
gle row. This parameter is fixed to t
• t (row refresh cycle). Required delay time to refresh a single
RFC
row. This parameter is fixed to t
• t (exit self-refresh mode). Required delay to exit the self-refresh
XSR
mode. This parameter is fixed to t
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
SDADDRMODE
A-51.
=t
RC RAS
=t
RFC RC
= t
XSR RC
External Port
bit = 1) has the fol-
RCD
+ t cycles.
RP
cycles.
cycles.
+1
3-37