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To control the assertion sense of the
corresponding
TMxCTL
level) or set (causes a high assertion level).
When enabled, a timer interrupt is generated at the end of each period. An
ISR must clear the interrupt latch bit
and/or width values. In pulse width modulation applications, the program
can update the period and pulse width values while the timer is running.
When a program updates the timer configuration, the
must always be written to last, even if it is necessary to update only
one of the registers. When the
the ISR reads the current value of the
again. On the next counter reload, all of the timer control registers
are read by the timer.
To generate the maximum frequency on the
the period value to two and the pulse width to one. This makes the
signal toggle every 2
= 133 MHz:
PCLK
Maximum period = 2 × (2
If your application requires a more sophisticated PWM output
generator, refer to
Single-Pulse Generation
If the
bit is cleared, the
PRDCNT
the
signal. This mode can also be used to implement a well
TIMERx_O
defined software delay that is often required by state machines. The pulse
width (= 2 ×
TMxW
should be set to a value greater than the pulse width register.
At the end of the pulse, the interrupt latch bit (
timer is stopped automatically. If the
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register is either cleared (causes a low assertion
clock cycles as shown in
PCLK
31
– 1) × 7.5 ns = 32 seconds.
Chapter 7, Pulse Width
PWM_OUT
) is defined by the width register and the period register
Peripheral Timers
signal, the
TIMERx_O
and might alter period
TIMxIRQ
value is not subject to change,
TMxW
register and rewrite it
TMxW
output signal, set
TIMERx_O
Figure
Modulation.
mode generates a single pulse on
) is set and the
TIMxIRQ
bit is set, an active high pulse
PULSE
bit in the
PULSE
register
TMxW
TIMERx
16-9. Assuming
16-11
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