Table of Contents
Advertisement
Table 6-3. SPORT DAI/SRU Signal Connections
Internal Node
Inputs
SPORT5–0_CLK_I
SPORT5–0_FS_I
SPORT5–0_DA_I
SPORT5–0_DB_I
Outputs
SPORT5–0_CLK_O
SPORT5–0_FS_O
SPORT5–0_DA_O
SPORT5–0_DB_O
SPORT5–0_CLK_PBEN_O
SPORT5–0_FS_PBEN_O
SPORT5–0_DA_PBEN_O
SPORT5–0_DB_PBEN_O
SRU SPORT Receive Master
If the SPORT is operating as receive ma ster, it must feed its master output
clock back to its input clock. This isrequired to trigger the SPORT's state
machine. Using SPORT 4 as an example receive master, programs should
route
SPORT4_CLK_O
operating as a transmitter in master mode.
SRU SPORT Signal Integrity
There is some sensitivity to noise on the clock (
sync (
SPORTx_FS
receiver. By correctly programming the signal routing unit (SRU) clock
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
DAI Connection
Group A
Group C
Group B
Group A, D
Group C, D
Group B, D
Group F
to
SPORT4_CLK_I
) signals when the SPORT is configured as a master
SRU Register
SRU_CLK1–0
SRU_FS0
SRU_DAT2–0
. This is not required if the SPORT is
SPORTx_CLK
Serial Ports
) and frame
6-7
Advertisement
Table of Contents
