Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 663

When clocked internally, the clock source is the processor's peripheral
clock ( ). The timer produces a waveform with a period equal to 2 x
PCLK
and a width equal to 2 ×
TMxPRD
through the
TMxPRD30–0
Operating Modes
The three operating modes of the peripheral timer; PWM_OUT,
WDTH_CAP, and EXT_CLK, are described in
lowing sections.
Table 16-4. Timer Signal Use
Register PWM_OUT Mode
Settings
MODE
TIMEN
PULSE
PRDCNT
IRQEN
Period
Width
Counter
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
TMxW
and the
TMxW30–0
01 = Output PWM Wave-
form
1 = Enable & Start Timer
0 = Disable Timer
1 = Generate High Width
0 = Generate Low Width
1 = Generate PWM
0 = Single Width Pulse
1 = Enable Interrupt
0 = Disable Interrupt
WO: Period Value
WO: Width Value
RO: Only if not enabled
Counts down on PCLK
Peripheral Timers
. The period and width are set
bits. Bit 31 is ignored for both.
Table 16-4
WIDTH_CAP Mode
10 = Input Waveform
1 = Enable & Start Timer
0 = Disable Timer
1 = Measure High Width
0 = Measure Low Width
1 = Measure Period
0 = Measure Width
1 = Enable Interrupt
0 = Disable Interrupt
RO: Period Value
RO: Width Value
RO: Only if not enabled
Counts up on PCLK
and the fol-
EXT_CLK Mode
11 = Input Event
1 = Enable & Start Timer
0 = Disable Timer
1 = Count at event rise
0 = Count at event fall
Unused
1 = Enable Interrupt
0 = Disable Interrupt
WO: Period Value
Unused
RO: Only if not enabled
Counts down on Event
16-7