Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 179

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It should be noted that the DDR2 DLL acts as an interface for only the

signals mentioned above and the clock output (

does not operate on the

During a memory read, the data from the DDR2 memory (SSTL-18 level)

is converted to the core voltage logic level inside the DDR2 memory I/O

pads. This is captured by the DDR2 DLL using precise delays on the data

provided to the controller. During a memory write, the data strobe

) signal to the DDR2 is delayed by a fixed amount. Note

there are stringent timing requirements between the DDR2 DLL and the

Figure 3-11. DDR2 Controller

The DDR2 DLL controls the setting of the delay for the data capture. The

delay elements and DLL in the block are sensitive to process, voltage and

temperature variations as well as to the operating frequency.

The DDR2 controller enables either the read or the write path in the

memory I/O. Read data is sent by the DDR2 DRAM on both the rising

ADSP-214xx SHARC Processor Hardware Reference

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) line in accordance with the JEDEC specification and

and command lines (

External Port

) to the DDR2, it

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