Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 584

S/PDIF Receiver
DIR_I
(BIPHASE STREAM)
Figure 13-8. S/PDIF Receiver Block Diagram
The input to the receiver (
contain two audio channels (compressed or linear PCM) or non-audio
data. The receiver decodes the single biphase encoded stream, producing
2
an I S compatible serial data output that consists of a serial clock, a
left-right frame sync, and data (channel A/B). It provides the programmer
with several methods of managing the incoming status bit information.
The S/PDIF receiver receives any S/PDIF stream with a sampling fre-
quency range of 32 kHz – 15% to 192 kHz + 15% range.
The channel status bits are collected into memory-mapped registers, while
other channel status and user bytes must be handled manually. The block
13-14
www.BDTIC.com/ADI
PROCESSOR
PLL
LRCLK_REF_O
DIGITAL
PLL
LRCLK_FB_O
INT
PLLCLK
512 x FS
FEEDBACK
DIVIDER = 512
BIPAHSE
DECODING
REFRAMING
LOGIC
) is a biphase encoded signal that may
DIR_I
ADSP-214xx SHARC Processor Hardware Reference
OFF-CHIP
REFIN
ANALOG
PLL
FBIN
CLK
SPDIF_EXTPLLCLK_I
STREAM
PREAMBLE
DIR_CLK_O
DIR_FS_O
DIR_DAT_O
DIR_TDMCLK_O
S/PDIF RECEIVER