Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 922

Peripheral Registers
Table A-57. MLB_DCCR Register Bit Descriptions (RW) (Cont'd)
Bit Name
29–28 MCS
30 LBM
31 MDE
System Status Register (MLB_SSCR)
This register, shown in
system software to monitor and control the status of the MLB network.
The register is updated once per frame by hardware during the MLB sys-
tem channel. The bits of this register are not valid until the ADSP-214xx
is locked to the MLB interface (except for the bits associated with MLB
lock and unlock,
before the start of the next MLB frame to prevent the current frame status
from being lost.
15
SSRE
System Service Request Enable
SDMU
System Detects MLB Unlock
SDML
System Detects MLB Lock
SDSC
System Detects Subcommand
Figure A-46. MLB_SSCR Register
A-96
www.BDTIC.com/ADI
Description
MLB Clock Select.
00 = 256Fs – supports 8 quadlets per frame
01 = 512Fs – supports 16 quadlets per frame
10 = 1024Fs – supports 32 quadlets per frame
11 = reserved
Loopback Mode Enable.
0 = Loopback disabled
1 = Loopback enabled
MLB Enable.
0 = MLB disabled
1 = MLB enabled
Figure A-46
and ). System software must service events
SDMU SDML
14 13 12 11 10 9 8 7
ADSP-214xx SHARC Processor Hardware Reference
and described in Table
6 5 4 3 2 1 0
SDR
System Detects Reset Command
SDNL
System Detects Network Lock
SDNU
System Detects Network Unlock
SDCS
System Detects Channel Scan
A-58, allows