Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 810

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Pin Multiplexing

During the boot process, word packing (for example 8 to 32-bit) is per-

formed over the SPI. In other words, the kernel is not loaded directly with

256 x 48-bit words, instead it is loaded with 384 x 32-bit 'packed words'

(2-column access). The same physical memory for instruction boot is

loaded via DMA in normal word (NW) 2 column. However, after booting

the same physical memory region is fetched by the sequencer in NW

3-column. For example the loader kernel itself has a NW 2 columns count

of 256 x 3/2 = 384 words but the kernel is executed with 256 instruction

Note that the interrupt vector table addresses are defined as:

IVT_Start_Addr

Pin Multiplexing

The SHARC processors provide extensive functionality using a low pin

count (reducing system cost). They do this through extensive use of pin

multiplexing. The following sections provide information on this feature.

Although the processors have the efficient and flexible DAI and DPI rout-

ing options, there are also I/O pins which are shared by some peripherals.

The following sections discusses these options.

On the ADSP-2146x processors the AMI and DDR2 interfaces are

completely independent (not multiplexed). Only the AMI control-

ler address/memory selects and data pins are shared and therefore

all pins discussed in this section refer to the AMI controller.

Core FLAG Pins Multiplexing

This module also includes the multiplexers of the

memory select

signal of the core timer or as a memory select

www.BDTIC.com/ADI

= 0x8C000 and

IVT_End_Addr

pins can act as core

pin) and the

ADSP-214xx SHARC Processor Hardware Reference

pin can act as a core

pins shown in

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