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phase-locked loop. Note that the goal in selecting a particular clock ratio
for an application is to provide the highest permissible internal frequency
for a given
CLKIN
rates, see the appropriate product data sheet.
Table 22-2. Selecting Core to CLKIN Ratio (ADSP-2146x)
Clock Ratios
(CLK_CFG Pins)
2
6:1
16:1
32:1
1 For operational limits for the core clock frequency see the appropriate product data sheet.
2 For ADSP-2147x and ADSP-2148x models, the ratio is 8:1.
Operating Modes
The following sections provide information on the various options for
clock operation.
Bypass Mode
Bypass mode must be used if any runtime VCO clock change is required.
Setting the
PLLBP
the core runs at
frequency, (which may take 4096
cleared to release the core from bypass mode.
"Back to Back Bypass" on page 22-17.
Only VCO frequency changes require bypass mode, therefore this
mode is not intended as a standard operating mode.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
frequency. For more information on available clock
Typical Crystal and Clock Oscillators Inputs
12.500
16.667
N/A
100
200
266.66
400
N/A
bit bypasses the entire PLL circuitry. In bypass mode,
speed. Once the PLL has settled into the new VCO
CLKIN
CLKIN
Power Management
25.000
33.333
1
Core CLK (MHz)
150
200
400
N/A
N/A
N/A
cycles) the
PLLBP
For more information, see
40.000
50.000
240
300
N/A
N/A
N/A
N/A
bit may be
22-7
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