Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 937

Table A-68. MLB_CSCRx Register Description (RO) (Cont'd)
Bit Name
10 STS10
(DMA)
11 STS11
(DMA)
15–12 Reserved
16 RDY
(RW)
17 GIRB
(RW)
29–18 Reserved
30 BF
31 BM
Channel x Current Buffer Configuration Registers
(MLB_CCBCRx)
These read-only registers, described in
itor the address pointer and buffer length of the current DMA buffer in
internal memory when the logical channel is configured in DMA mode.
When configured in I/O mode, this register implements the Rx data
buffer. The definition of the bit fields in this register vary depending on
the selected channel type.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Description
Previous Buffer Done. Indicates that the last quadlet of the Previous Buffer has
been successfully transmitted or received. The setting of this bit generates a mask-
able channel interrupt to system software. This bit is valid for all channel types.
Reserved in I/O mode.
Previous Buffer Start. Indicates the first quadlet of the Previous Buffer has been
successfully transmitted or received. The setting of this bit generates a maskable
channel interrupt to system software. This bit is valid for all channel types.
Reserved in I/O mode.
Next Buffer Ready (DMA Mode). This bit is reserved for I/O mode.
0 = Next buffer ready for ping-pong DMA. Hardware clears this bit after the buf-
fer begins to be processed.
1 = Next buffer ready for circular buffer DMA. Software should clear this bit only
when buffer processing needs to be stopped.
Reserved = For Synchronous Channels.
0 = Generate isochronous receive break for isochronous channels.
1 = Generate break for asynchronous and control channels.
Channel x Buffer Full. When set, buffer is full.
Channel x Buffer Empty. When set, buffer is empty.
Registers Reference
Table A-69, allow software to mon-
A-111