Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 64

Manual Contents
• Chapter 15,
Describes the operation of the serial peripheral interface (SPI) port.
SPI devices communicate using a master-slave relationship and can
achieve high data transfer rate because they can operate in
full-duplex mode.
• Chapter 16,
Describes three identical 32-bit timers that can be used to interface
with external devices.
• Chapter 17,
Describes the 18 stage serial in, serial/parallel out shift register.
• Chapter 18,
Describes the digital watch features.
• Chapter 19,
Describes software watchdog function which can improve system
reliability by forcing the processor to a known state.
• Chapter 20,
Describes the operation of the Universal Asynchronous
Receiver/Transmitter (UART) which is a full-duplex peripheral
compatible with PC-style industry-standard UART.
• Chapter 21,
The two wire interface is fully compatible with the widely used I
bus standard. It is designed with a high level of functionality and is
compatible with multi-master, multi-slave bus configurations.
• Chapter 22,
Describes system design features of the ADSP-214xx processors.
These include power, reset, clock, JTAG, and booting, as well as
pin multiplexing schemes and other system-level information.
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"Serial Peripheral Interface Ports"
"Peripheral Timers"
"Shift Register – ADSP-2147x"
"Real-Time Clock—ADSP-2147x"
"WatchDog Timer – ADSP-2147x"
"UART Port Controller"
"Two Wire Interface Controller"
"System Design"
ADSP-214xx SHARC Processor Hardware Reference
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