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Operating Modes
16-Bit Receive FIFO Register
The TWI 16- bit FIFO receive register (
holds a 16-bit data value read from the FIFO buffer. Although peripheral
bus reads are 32 bits, a read access to the
two receive data bytes from the FIFO buffer. To reduce interrupt output
rates and peripheral bus access times, a double-byte receive data access can
be performed. Two data bytes can be read, effectively emptying the receive
FIFO buffer with a single access.
RCVDATA16(23–16)
Byte1
Figure 21-10. 16-Bit Receive FIFO Register
The data is read in little-endian byte order where byte 0 is the first byte
received and byte 1 is the second byte received. With each access, the
receive status (
TWIRXS
cate it is empty. If an access is performed while the FIFO buffer is not full,
the core waits until the receive FIFO buffer is full and then completes the
read access.
Operating Modes
The following sections provide information on the operation modes of the
interface.
General Call Addressing
The TWI controller always decodes and acknowledges a general call
address if it is enabled as a slave (
using the
TWIGCE
setting of the
GCALL
21-14
www.BDTIC.com/ADI
15
14
13
12
11 10
9
8
) field in the
TWIFIFOSTAT
TWISEN
bit. General call addressing (0x00) is indicated by the
bit, and by the nature of the transfer, the TWI con-
ADSP-214xx SHARC Processor Hardware Reference
) shown in
RXTWI16
register can only access
RXTWI16
7
6
5
4
3
2
1
0
register is updated to indi-
) and if general call is enabled
Figure 21-10
RCVDATA16 (7–0)
Byte0
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