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DDR2 DRAM Controller (ADSP-2146x)
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Single bank access
Figure 3-16. Single Versus Multibank Access
Force Activation Window
Traditionally, SDRAM has operated with a maximum of 4 internal banks.
However, with DDR2 some higher-density devices will support 8 individ-
ual banks. For this reason, JEDEC has limited the number of banks that
may be activated within a set period.
DDR2 devices support a new timing parameter called four active banks
window (t
). This is the minimum amount of time that must pass
FAW
before more than four ACTIVE (ACT) commands may occur. It is accept-
able to have more than 4 banks open simultaneously, but the additional
ACT command(s) must be spaced out past the t
shown in
Figure
To satisfy t
FAW
Furthermore the controller supports four external memory selects contain-
ing each DDR2. All external banks (
support, so the maximum number of open pages is 8 x 4 = 32 pages.
3-72
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Bank A
Bank B
Bank C
Bank D
3-17, t
for the fourth opened bank is complete at T8.
RCD
(min), the fifth ACT command cannot occur until T11.
ADSP-214xx SHARC Processor Hardware Reference
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Multibank access
(min) window. As
FAW
) provide multibank
DDR2_CSx
Bank A
Bank B
Bank C
Bank D
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