Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 851

DDR2 Control Register 0 (DDR2CTL0)
The DDR
DDR2CTL0
ciated with the DDR configuration.
corresponding control bit definitions. The
,
SREF_EXIT DDR2SRF
next clock edge cycle after they are set.
31 30
DDR2MODIFY (31–28)
Read Modifier
DDR2OPT
Read Optimization Enable
SREF_EXIT
Self Refresh Exit
DDR2BUF
Enable Pipeline
FEMR
Force EMR Register Write
FLMR
Force MR Register Write
15
DDR2PSS
Powerup Start
DDR2ADDRMODE
Address Mapping Mode
FDLLCAL
Force On-chip DLL
Calibration
FEMR2
Force EMR2 Register
Write
DDR2RAW (11–9)
DDR2 Row Address Width
Figure A-9. DDR2CTL0 Register
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
register includes the programmable parameters asso-
, and bits are automatically cleared on the
DDR2PSS
29 28 27 26 25 24
14 13 12 11 10 9 8 7
Registers Reference
Figure A-9 and Table A-11
,
FEMRx FLMR
23 22 21 20 19 18 17 16
6 5 4 3 2 1 0
DIS_DDR2CTL
DDR2 Enable
DIS_DDR2CLK1
Disable DDR2 Clock 1
DDR2BC (3–2)
DDR2 Bank Count
DIS_DDR2CKE
DDR2 CKE Disable
DDR2CAW (7–5)
Bank Column Address Width
SH_DLL_DIS
Internal DLL Disable
show the
, , , ,
FDLLCAL FAR FPC
DDR2WDTHx16
Must always be set to 1 for
ADSP-2146x.
FEMR3
Force EMR3 Register Write
DDR2SRF
Self Refresh Entry Mode
DDR2ORF
Disable Auto Refresh
Mode
FAR
Force Auto Refresh
FPC
Force Precharge
A-25